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Altera_Forum's avatar
Altera_Forum
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13 years ago

continuous averaging using VHDL

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is: process (clk, reset) begin if (reset = '1') then state<=idle; out-v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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@kaz

If I dont put '0', I get the following error. Should I reduce subtractor bits?

Error (10344): VHDL expression error at adc_cntrl.vhd(160): expression has 12 elements, but must have 13 elements.

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sub_result <= resize(signed(data_in),13) - signed(stage(31));

if you are not averaging both ADC data in parallel then you can switch between them at signal stage: 


if avg_1 then 
   stage(1) <= adc1;
elsif avg_2 then
   stage(1) <= adc2;
end if;