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Altera_Forum's avatar
Altera_Forum
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12 years ago

continuous averaging using VHDL

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is: process (clk, reset) begin if (reset = '1') then state<=idle; out-v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Couple of comments:

Why are you appending '0' on the LSB? thats like a multiply by 2, and as it is signed, it then uses the MSB as the sign bit. I think you mean:

('0' & data_in(11 downto 0);

Unless data_in is signed, then you need:

(data_in(11) & data_in(11 downto 0));

And as a general comment:

Why is type1 an array of std_logic_vector? why not make your life easier and make it an array of signed, then you dont need all the type conversions.