continuous averaging using VHDL

@kaz

Just as an example, I am doing continuous averaging for 4 values. Can you check if my approach is correct.

process (clk, reset)
begin
    if (reset = '1') then 
    state<=idle;
    out_val=0;
    elsif(rising_edge(clk)) then
    case state is
when idle =>
    if req='1' then 
    state= out_1;
    end if;
when out_1 =>
    if done='1' then
    out_val<=data_in (11 downto 0);
    i_valid <=1;
    state <= done_st;
    endif;
    when done_st =>
    ack <='1';
    state <= idle;
    when others =>
    state <= idle;
    end case;
    end if;
    end process;
process begin
wait until rising_edge(clk);
valid1 <= i_valid;
o_valid <= valid1;
end process
-- i_valid is control bit and enables when input data is valid
process begin
wait until rising_edge(clk);
if reset = ’1’ then
idx <= "0001";
elseif 
valid1 = ’1’ then
idx <= idx rol 1;
end if;
end if;
end process;
process begin
     wait until rising_edge(clk);
     for i in 3 downto 0 loop
     if (i_valid = ’1’)  and (idx(i) = ’1’) then
     M(i) <= out_val;
     end if;
     end loop;
     end process;
mem_out <= M(0) when idx(0) = ’1’else 
           M(1) when idx(1) = ’1’else 
           M(2) when idx(2) = ’1’else 
           M(3);
add_sub <= sum - mem_out when valid1 = ’1’
else sum + mem_out;
process begin
wait until rising_edge(clk);
if i_valid = ’1’ or valid1 = ’1’ then
sum <= add_sub;
end if;
end process;

sum is the output average value. The above code works if I have unsigned numbers. But I want to average the std_logic_vector. The data_in is defined as: data_in: in std_logic_vector (11 downto 0);

Kindly help me in solving this issue. Please modify the above code so that I can get continuous averaging values for vector 'out_val'.

Many Thanks.