constraints

My code includes the follow lines :

reg [9:0] cnt ='b0;
reg en ='b0;
always @(posedge clk10 )
begin
cnt = cnt + 1'b1 ;
if (cnt == 10'b1111111111 )
en = !en ;
end
assign A = en ? 1'bz : 1'b0 ;

In addition , my qsf file include the line :

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *

this code should implement other drive each 1ms

1ms - high Z

1ms- '1b0

when I test I in the lab - the scope show steady 1'b0 ( I use pull up transistor to recognize 1'b0 / 1'bz )

Then - I found out warnings in the fit.plan.rpt

Warning (176225): Can't pack node en_Z~_Duplicate_1 to I/O pin File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840
Warning (176260): Can't pack node en_Z~_Duplicate_1 and I/O node en_RNO -- one node must be a logic cell and one must be an I/O cell File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840

Can you explain what is wrong in my simple code ? what should I change in the code in order to prevent from this warning

Mybe when I fix it - my high Z implemetation will work

Yishay