Constraints for SRAM with ext. feedback PLL

Hello,

I've got a board with Stratix V and Synchronous RAM on it. This is how my design looks like:

First PLL is a Normal mode PLL that clocks desing logic. The second PLL has an external feedback an it is used to clock an external Synchronous SRAM.

Length of feedback trace and Address/DQ traces are the same. This fact makes both clocks (RAM clock and internal one) phase aligned.

My question is:

How do I constraint (TimeQuest constraints) both Address and DQ outputs? (set_input_delay, set_output_delay).

What clock should I use for constraining outputs/inputs to/from RAM?

How do I "tell" TimeQuest about phase alignement mechanism?

Thank you,

Alex

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