Constraints for Multiplexed Clocks

I'm not sure why you're using get_nets. You should be pointing to the input port for the base clock:

create_clock -name base_clk -period 13.42 [get_ports {base_clk}]

You also probably need to make clk_mux a generated clock. It might even need to be two generated clocks, clk_mux_1x and clk_mux_2x, if the output of the mux is used as the source or destination clock and clk_1x or clk_2x are used at the other end. In other words, you need to think of all possibilities that you are using for the source and destination clocks throughout your design.

As for your question, if all possibilities of source and destination clock are valid throughout your design (1x -> 2x, 2x -> 1x, 1x -> 1x, 2x -> 2x), then you don't need any false paths or clock group timing exceptions. Those are only needed when clock crossings in either direction between 1x and 2x should not be analyzed. What you do need, if you don't use separate registers to handle the transfers between the 1x and 2x clock domains, are multicycle timing exceptions. For going from 2x to 1x, you'll need start multicycle to move the launch edge and for going from 1x to 2x you may need end multicycle to move the latch edge used in the 2x domain to match up with the 1x domain. So it might look like this:

set_multicycle_path –from clk_2x –to clk_1x –setup –start 2

set_multicycle_path –from clk_2x –to clk_1x –hold –start 1

set_multicycle_path –from clk_1x –to clk_2x –setup –end 2

set_multicycle_path –from clk_1x –to clk_2x –hold –end 1

This Wiki page gives a good rundown of multicycle:

http://www.alterawiki.com/wiki/timing_constraints