Constraining the delay on an asynchronous path

Hi there!

I have a Stratix III FPGA connected to a DSP, and I'm trying to simulate (via the Quartus simulator) the latency of a read command from the DSP. The FPGA is connected to a 64 bit bidirectional data bus, address bus, CS and read enable (the interface is synchronous). Whenever a specific address appears on the address bus, along with a CS and read activity, the FPGA outputs data to the data bus (when one of the terms do not apply, the FPGA switches the data bus to be input). The logic inside the FPGA is asynchronous to the interface clock (the clock is 120MHz).

What I have noticed is that the simulation shows me that when I issue a read to the FPGA (address, CS and read enable) for a time of 1 clock cycle, the FPGA outputs the data after a time which is 2 interface clocks cycles (although it is coded asynchronously, meaning the delay is unrelated to the clock). Is it intentional? Can I control this delay? (I'd obviously want this delay to be known and similar for every compilation).

I'd also like to add that im using the classic timing analyzer.