New ContributorWhile I know how to constraint regular I/O delays (set_input_delay min/max and set_output_delay min/max), when it comes to MII-related timing I am a bit confused.
The datasheet of the PHYs have the following timing specs.
RXDV, RXD, RXCLK and TXCLK are inputs to the design, while TXEN and TXD are outputs of the designs.
How exactly should I constrain the timing constraints correctly?
Regular ContributorHello,
Thank you for using Intel Communities. Please allow some time while I investigate your problem.
Regards,
Nurina
Regular ContributorHello,
May I know which device you are targeting?
Regards,
Nurina
Regular ContributorAlso, which PHY are you using?
New ContributorI am using Microchip LAN8710 (Timing diagram on page 73 https://ww1.microchip.com/downloads/en/DeviceDoc/8710a.pdf) to interface on my Arria 10 devices.
Regular ContributorThanks, and which Quartus version are you using?
Regards,
Nurina
New ContributorI am using Quartus Pro 22.4
Regular ContributorHello,
Sorry for the late response.
Clocks:
Add create_clock for both RX and TX clocks to input port.
RX signals:
set_input_delay -clock MII_RXCLK -max 28.0 [get_ports {RXDV RXD*}] -add_delay
set_input_delay -clock MII_RXCLK -min 12.0 [get_ports {RXDV RXD*}] -add_delay
TX signals.
set_output_delay -clock MII_TXCLK -max 12.0 [get_ports {TXEN TXD*}] -add_delay
set_output_delay -clock MII_TXCLK -min 0 [get_ports {TXEN TXD*}] -add_delay
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Regular ContributorHi,
May I know if above solution helped?
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
