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Did you run "Report Unconstrained Paths" and "Check Timing" as I suggested? If they don't list anything unconstrained, then TimeQuest is analyzing all internal paths. You don't add constraints specifically to make TimeQuest analyze micro tsu and micro th.
Be sure you are analyzing with all timing models. If you are using just the slow model, you might be missing hold violations.
If this is Cyclone III or Stratix III, use derive_clock_uncertainty. If you didn't use that, your real slacks are less than what is currently being reported.
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Yes, i have run all TimeQuest reports and no warnings or errors occur in any of the timing models. My device is a Cyclone II. fmax is some 40% higher than the clock frequency used so there should be plenty of margin for the counter input to the 26-bit registers to stabilize.
I have checked in the RTL viewer and everything seems ok.
Does it *ever* happen that Quartus II or TimeQuest makes mistakes?
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