Honored Contributor
Honored ContributorI now have other internal signals that i suspect are not meeting timing (although not flagged by quartus II). I have an SDRAM FIFO Controller which implements a circular buffer. I have a read pointer and a write pointer, both 26 bits. These pointers are being updated in Verilog (write_pointer <= write_pointer + 26'd8) as words are being burst in chunks of 8 words from / to the SDRAM. The problem is that it looks like the new pointer value is not stabilized before the next clock edge comes around which results in the circular buffer incorrectly flags as full.
How can i add an SDC constraint for *internal* signals such that i can be confident that the micro tsu/th is met? The clock domain is meeting fmax requirements with some 50 MHz to spare.
