Constraining internal logic?

All clocks are constrained. My SDRAM outputs were however not properly constrained since i had a syntax error in the SDC lists (used comma between names instead of spaces). Perhaps this caused the timing to be off when i added the LAI configuration. I will do more testing to see if i can reproduce the error. It is possible that the SDRAM address was transferred incorrectly (which would explain the data loss).

I also have a lot of asynchronous data and control signals that are hooked up to a CPU that are flagged unconstrained. The CPU is executing off the same base clock as the FPGA so in theory the CPU and FPGA clocks are related but since i don't know the timing of I/O from the CPU i treat all these signals as asynchronous. I was planning to add synchronizers to all inputs from the CPU to the FPGA. All Input ports on the CPU (from the FPGA) should already contain synchronizers since they are regular I/O ports. Anything in addition i should think about?

Thanks,

/John.