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I have a bug somewhere in my design that causes data loss. All I/O has properly been constrained and verified ok. When compiling in LAI (Logic Analyzer Interface) configuration in my design (so i can debug the problem) i can no longer reproduce the issue. This tells me that internal timing changes when enabling the LAI.
The Altera documentation states that *all* paths should be constrained (even internal paths). How do i handle this? I would assume that Quartus II *knows* the tsu and th of all internal registers and that I, as user, would not have anything useful to add to the equation. Is it required to add a "default" tsu and th to all internal paths?
I'm using Timequest.
Thanks,
/John.
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Hi John,
did you try different Quartus Versions?
By implemeting Signaltap or the Logic Analyzer Interface and use of pre_synthesis nodes you do not change only the routing and placement. The synthesis results are also different.
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