Honored Contributor
Honored ContributorI am interested in the use of a 'notaclock' to allow async read paths to be constrained
I have a register block in my CPLD that is accessed to by a processor using a fairly standard async bus with addr, /cs, /rd, /wr and data lines I find that I can do the following quite happily: either... a) Constrain my write timings by defining /wr as a write clock with timings that match my processor, and set_input_delays on the addr and cs that match the write cycle waveform from the processor or... b) Constrain my read timings by using set_max_delay -from[get_ports{/cs /addr /rd}] -to[get_ports{data}] <processor's required read decode Tpd time, ns> But when I put both together, the set_input_delays used to constrain writes get added to the read decode timings, so my read decode time appears much longer than it really is Worse, I cannot just add matching extra margin to set_max_delay in order null the unwanted set_input_delays. This is because some of my registers are write/read so have a write clock associated (and so set_input_delays times are added to the read decode logic), but some regs are read only, so have no delays added Q: Can I use a 'notaclock' to trick the set_max_delay constraint to just 'work' and time the async addr, /cs, /rd --> data decode timing and get rid of the unwanted write delay additions? Is there any other simple way around these problems that I have missed?
