Honored Contributor
Honored ContributorThis all just don't work!!:mad:
The good news is that I found an error in my design: The Component which receives the data had an asynchronous reset which preventet the inputs from using fast IO registers. => I didn't really need that reset so I deleted it. Well, I tried a lot now: I think the best way must be a PLL in the receiving clock set to Source-Synchronous mode. The Input Pins are set to PLL-Compensated and "Input to Register Delay"-Option is set to 0. Like it is described here: http://www.altera.com/support/kdb/solutions/rd04042007_404.html But when I receive some data over this, I get a lot of errors. When I look at the Inputs of the first component which receives the Data (via LAI), there Is a huge skew in the Datas (about 2ns). Why is there such a skew? I tried to set up a set_max_skew constraint to the Inputs, but all the fitter sais is that it can't find a matching port/keeper/whatever. And on top of that I have the suspicion that some busses WITHIN my design also have a skew. (Perhaps the data are already send incorrectly) Is there a need/way to constrain busses within the fpga with set_max_skew?
