Constraining a source synchronous, SDR, center aligned Input

The only way for me to have a look on the received Signals inside the FPGA is the Logic-Analyzer-Interface (LAI).

It always showed me, that the data are almost edge-aligned to the clock. I meassured the Bus-Signals on the Ethernet-Serdes and they were proberly center-aligned.

I then wathed the Output of my 8b10b-Decoder and often it decoded Data where no Data was sent. It also had a weird behaviour on it's control-signals (It decodes K28.5 to an IDLE-Signal).

Since I use the way with the PLL everything works fine and I can finally adjust the rising edge of the Clock to the Center of the Data.

So I will stay on this solution.

But now I have a little Problem:

The Fitter always shows me this warning:

Warning (15062): PLL "<MY_PLL>" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register

I set the Input-Pins (or Ports) to "PLL compensated" in the assignment editor. But how do I finally connect the Output of the PLL to them?

I thought this is made automatically.