Honored Contributor
Honored ContributorOK, I tried this. With no effect.
Now I'm trying something totally different: I implemented a PLL into the received clock and set it to source synchronous mode. Then I set the Input-Pins in the assignment editor to PLL compensated and also set them to "Input Delay from Pin to Input Register" = 0. This is described in the Device Handbook for cyclone IV in Chapter 5 "Source-Synchronous Mode". Now I finally have full control over the received clock to move it where I want. But I also have this warning: Warning (176264): Can't pack I/O cell SERDES_RD[4]~input -- no fan-out from combinational output port Quartus Help told me that I have enabled the "Fast Input Register"-Option in the Assignment Editor. NO, I HAVEN'T. I also tried to set "Fast Input Register" to Off in the Assignment-Editor. But the warning didn't disappear. When I remove the "Input Delay from Pin to Input Register"-Option, the warning disappears. BUT: The Fitter always tells me that the PLL Compensation Assignment is ignored. Is there something more I have to do? Like some global setting? In the SDC-File I tried to set the maximum skew of the Inputs with: set_max_skew -from [get_ports {SERDES_RD [*]}] -to * 0.100 (And some other Values) All with the same effect: the skew seems to be stucked at about 1.5ns. I don't get it. Do some of the constraints have to be enabled somewhere? Are they overwritten by some other setting?
