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Altera_Forum
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8 years ago

Constrained clock appears as unconstrained input

Hello, I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I loo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yes, I know that with PLL it works, but actually I'm trying to do without PLL, as board manufacturer states that at 50MHz no phase shift needed between SDRAM chip clock and SDRAM controller clock.

So is it possible without PLL ?