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Altera_Forum
Honored Contributor
Honored ContributorConstrained clock appears as unconstrained input
Hello, I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I loo...
Altera_ForumHonored Contributor
Honored ContributorYou should probably use a PLL to generate DRAM_CLK instead of just trying to route it through.
