Constrain SDR source-synchronous bidirectional interface

I've corrected the type in the clock constaints - they were correct in the original sdc.

One clarification: there is no output clock from the MAX10 to the MCU. Instead , the MCU supplies a constant 25MHz clock to which the data and control lines are synchronous both for writes (data from MCU to FPGA) and reads (data driven by FPGA).