Constrain SDR source-synchronous bidirectional interface

I don't see a generated output clock for the output interface. Using derive_pll_clocks is OK, but you still need a generated clock on the clock output port (and an associated false path for that output clock so it's not analyzed as a data path). The output delay constraints should reference this newly generated output clock, not an input clock. Also, you reference clocks named fsmc_vsck and fsmc_sck in the input/output delay constraints, but you named them just vsck and sck. Check your ignored constraints report because I'm betting it will list these as ignored.