Honored Contributor
Honored ContributorThanks, the code I posted was just an example of the clock tree structure. I'm not actually implementing the gate that way, the gate control signal is latched on the opposite edge as the gated clock active edge, to prevent glitches. How does the clock gate conversion play if the register already has an enable? I read somewhere that it only works if the enable is available, and I know many registers have an enable...
I've implemented the clock control blocks using altclkctrl. I think it's working but I'm getting a troubling warning. Info (176449): Merged following Clock Control Blocks Warning (176704): CLKCTRL has less registers on the enable (ena) path for some destinations, and consequently, it may have a slightly different behavior than expected Warning (176704): CLKCTRL has less registers on the enable (ena) path for some destinations, and consequently, it may have a slightly different behavior than expected Warning (176704): CLKCTRL has less registers on the enable (ena) path for some destinations, and consequently, it may have a slightly different behavior than expected I removed the node names that typically follow "CLKCTRL". The design is on a Stratix IV. I have my clock coming in on a dedicated clock pin driving GCLK11. This drives PLL_T1, which in the datasheet is stated to be able to drive GCLK12-15. The PLL C0 output is GCLK12, then the three altclkctrl outputs are GCLK13-15. I forced them onto these nets with GLOBAL_SIGNAL and GLOBAL_SIGNAL_CLKCTRL_LOCATION assignments. I have a C1 PLL output with 2x frequency driving a RCLK. The datasheet states that each GCLK has it's own CLKCTRL, so I'm wondering what this merge is all about. Is there an issue with picking up all the CLKCTRL inputs from the same PLL output? The three altclkctrl have separate enables, so I don't want them being replaced by a single gate... Thanks in advance for your help folks.