Constrain delay of internal paths

Your un-gated domain, which comes directly from the PLL, will just have the global clock tree for its delay. The gated clocks will have this original global clock tree(PLLs ALWAYs drive a global) and then it gets off and goes through a LUT, and then onto another Global. So those delays will be much longer. A few ideas:

- If the gated clocks don't match, you might neet to lock down the LUT location and the global buffer it drives so they're right next to each other. I thought the fitter would automatically do that, so only do it if you don't see it happening.

- You could make your "non-gated" clock look like it's gated, i.e. have it go through a LUT. Just have it go through a wire with a keep attribute on it. That will then make it go through the same type of long path that the three gated clocks are going through.

- Ideally, get rid of the gated clocks. You could:

a) Create clock enables that drive all the logic, rather than gate the clock.

b) Instantiate the altclkctrl block multiple times. So basically your PLL would have 4 outputs, all identical, but they would each drive a different altclkctrl megafunction, and you would then use the enable on that block to turn the clock on and off. This would put them all onto globals driven directly by the PLL, thereby matching skews.