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... is there some special constraints I can apply on my mem_addr[11] pin to pass all my timing requirements ?? (I don't think so...)
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You can't change the device's maximum toggle rate limit for your combination of I/O settings for pin location, I/O standard, drive strength, slew rate, and on-chip termination (not all devices have all these kinds of assignments). If you need the pin to be able to toggle faster, you need to change one of those things.
The constraints tell TimeQuest how fast the pin might toggle. You need the constraints to match the actual design behavior. If the pin really might toggle as fast as TimeQuest thinks based on the clock related to this data output, then changing the timing constraints is not a valid solution. There might be some trick you could do with SDC constraints if the data signal won't be toggling as fast as possible given the clock frequency of the register driving the pin, but the only thing that comes to mind (except maybe something with a multicycle exception) would make other things in the timing be constrained incorrectly. There are toggle-rate settings visible in the Assignment Editor and stored in the .qsf for other purposes (at least for certain device families), but I doubt that there is one used by TimeQuest (almost everything TimeQuest uses comes from .sdc files, not the .qsf).
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