Constrain DDR2 IP -- need help

Hi brad,

Thanks for all your hints.

You're right, 18 ps in the worst case is not relevant for my application.

But I wish fix that just for learning how to identify and resolve some timing errors. Just for playing with sdc files and timequest analyser.

I have check in the device handbook specification for my specific io pin (assigned for mem_addr[11]) and with its clock rate and derating factor, I'm able to retreive required pulse width (3.018 ns).

This is because it's a dedicated output clock pin. For all others pins interfacing with DDR (using standard I/O pin), the minimum pulse width is 2.718 ns.

It's really strange because a dedicated output clock can not run faster than a simple standard output pin... ?!

So, before closing the subject, is there some special constraints I can apply on my mem_addr[11] pin to pass all my timing requirements ?? (I don't think so...)

Now, my simple DDR2 design is fully constraint, so I will try to make the same with my TSE - NIOS II - DDR2 design... !

I will come back later if I have more questions about timing contraints.

And yet one time, thank you very much for your answers and your rapidity.

Se you!