Constrain DDR2 IP -- need help

Up!

Bad news (for me!).

All my assignments seems to be ok and all pins of the mem_addr bus have the same assignments (exactly the same).

mem_addr

[*] :I/Os standard : SSTL-18 Class I

Current strength : Maximal current

Output Pin Load : 10 pF

I use PCI Express dev board with stratixx II GX. Interface between DDR2 and FPGA don't use ODT but external terminations. So the tcl script generated by the mega wizard is not good for my board (because it use ODT functionnality)

In the AN328, I found an example of implementation of DDR2 HP IP on the same board I use. (http://www.altera.com/literature/an/an328.pdf)

So I follow all the application note recommandations for applying constraints (see AN328 page 36/37/38). And the result, after compilation is the same as before.... => minimum pulse width error on mem_addr[11]

The only thing I notice is that mem_addr[11] is on the clk5n out pin and others mem_addr

[*] pins are on standard out pin (B8_IOxx). Is that important or not ?? Does I apply some specific constraints because of the clk5n pin ?

Do you want I post my entire project in order to help you to resolve my issues ?

Thanks in advance for your help!