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Altera_Forum
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17 years ago

Constrain DDR2 IP -- need help

Hi, I need your help for constrain my design based on the DDR2 HP IP from Altera. Actualy, I'm really a newbie in this particular step. I never have manually constrain a design. Well,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Ok. Thank you Brad for reply. I will check all my assignments, especially for the mem_addr bus and mem_addr[11]. Maybe something goes wrong here!

Another question: you say that the specifications for toggle rate for each I/O standard are in the device handbook. But I have search in the stratix II gx handbook and I didn't found them ?!

Could you tell me in which chapter / section have you find theses informations. Thanks you very much.

I will keep you inform for my problem.

See you.

Fabrice.