Constrain DDR2 IP -- need help

The "Minimum Pulse Width" violation with type "Port Rate" for mem_addr[11] means that the actual toggle rate based on the 3 ns actual width is too fast relative to the 3.018 ns required width for the combination of I/O standard and drive strength. (The specs for toggle rate for each I/O standard are in the device handbook.)

Do you have something different shown in the Assignment Editor for this one device pin compared to the other mem_addr[*] pins, which have a 2.708 ns required width?

When you generated the DDR2 MegaCore, you should have gotten generation messages that told you to run a .tcl script to set up the assignments like I/O standard.