Honored ContributorI am trying to implement a shifter with the max shifting bits being L=8. I could: 1. use three D blocks in series (L can be represented by three bits). Therefore, the shifting can be done in 3 clock cycles. 2. use combinational logic with several MUX (case statement in Verilog). Any ideas on the cons and pros in this situation?
Honored ContributorHi, I hardly understand :
you want for example to shift right "10101110" by L=4, which becomes "11111010" (without forgetting to fill the sign of the data as you wanted arithmetic) . the number of shifting L can vary, right ? Several ways to make that : In one clock, you can extend "10101110" to "111110101110" and take the first 8 bits. A begin of an idea. In L=4 clocks, you can shift one bit at a time and use counter to count L=4 shifting --- Quote Start --- use three D blocks in series --- Quote End --- to shift max 8 bits ?, how do you schematize that ? Case statement : hope the synthesizer will be clever, otherwise it will create MUX.
