Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI'm not familiar with this development kit, but you can simply connect two output addres buses into one in FPGA. For example:
entity SRAM_driver is
port
(
...
address_bus_1 : out std_logic_vector(15 downto 0);
address_bus_2 : out std_logic_vector(15 downto 0);
...
);
end SRAM_driver;
architecture behavioral of SRAM_driver is
...
signal internal_address_signal : std_logic_vector(15 downto 0);
...
begin
...
...
address_bus_1 <= internal_address_signal;
address_bus_2 <= internal_address_signal;
...
...
end behavioral;