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Honored Contributor
Honored ContributorConnecting HPS to FPGA DDR3 takes up all the address space
Hello, Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3...
Altera_ForumHonored Contributor
Honored ContributorYes, 0xC0000000 is the fixed base address of the FPGA subsystem components accessed by the H2F_AXI_MASTER.
