Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorConnecting HPS to FPGA DDR3 takes up all the address space
Hello, Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3...
Altera_ForumHonored Contributor
Honored ContributorSo for example:
1. If the HPS writes to its address 0xC000_0000 the data will appear in whatever is connected to address 0x0000_0000 on the FPGA ? 2. If the HPS writes to its address 0xC000_1000 the data will appear in whatever is connected to address 0x0000_1000 on the FPGA ?
