Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorConnecting HPS to FPGA DDR3 takes up all the address space
Hello, Using QSYS, I connected the HPS of a Cyclone V SOC to a DDR3 Controller on the fabric side via the HPS's H2F_AXI_MASTER bus. The DDR3 Controller is assigned address: 0x0000_0000 to 0x3...
Altera_ForumHonored Contributor
Honored ContributorSee the address map in the documentation:
https://www.altera.com/hps/en_us/cyclone-v/hps.html#topic/sfo1418687413697.html
