Connect split bus in verilog to output

Thank you very much, it works, now :) It is also much simpler and logical. For anyone stumbling upon this question the final code is:

module Tau2_LVDS(
input rx_inclock,
input  rx_in,
output rx_outclock,
output  data_out,
output sync_frame_start,
output sync_line_valid,
output sync_data_invalid
);
wire  sync_decode_signal;
  tau2_sync_decode sync_decoder_inst(
    .sync_in(sync_decode_signal),
    .sync_frame_start(sync_frame_start),
    .sync_line_valid(sync_line_valid),
    .sync_data_invalid(sync_data_invalid)
);
	
	tau2_lvds_deser tau2_lvds_deser_inst(
	.rx_in(rx_in),
	.rx_inclock(rx_inclock),
	.rx_out( {data_out, sync_decode_signal }),	
	.rx_outclock(rx_outclock)
	);
endmodule