Connect external clock via non-dedicated pin to PLL on Cyclone 10 LP

Hi,

As per the user guide, the PLL can be driven by a GCLK, but there is still a restriction.

"This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK. An internally-generated global signal cannot drive the PLL."

Referred from https://www.intel.com/content/www/us/en/docs/programmable/683777/current/pll-architecture.html note (2) below diagram.

The GCLK network can be accessed by dedicated inputs as mentioned in following page: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/gclk-network-sources.html

As clearly mentioned above, "An internally-generated global signal cannot drive the PLL", so this restriction remains.

One possible way for you is that if there is another PLL in your design, you may try to use that to drive this PLL through clock control block.

Regards