Forum Discussion
Thanks sstrell,
unfortunately, it seems not possible on Cyclone 10 LP:
If I directly connect the pin to the PLL I get:
Error (176554): Can't place PLL [...] -- I/O pin [..] (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device
If I add some combinational logic (inverter) I get:
Error (15065): Clock input port inclk[0] of PLL [..] must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
Info (15024): Input port INCLK[0] of node [..] is driven by [..] which is COMBOUT output port of Combinational cell type node [..]
(I replaced signal names by "[..]")
The latter error message also shows up if I use "pin - inverter - global - pll", although "pin - inverter - global" is usually valid and plls can be driven by globals.
The check seems to be implemented in Quartus and my question is if there is a way round.
Stefan