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Altera_Forum's avatar
Altera_Forum
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12 years ago

connect between sub-blocks at the same and differentE component

Hi ,

i want to connect the control signal - Seed_En (attached file) that his source block is LockStateMachine to :

a. The sub-blocks PN_transmitter at the same component - Rx .

do i need to define the instantiation of the Seed_EN at the Rx block or at LockStateMachine block ?

b. The sub-blocks PN_transmitter at different component - Tx .

do i need to define the instantiation of the Seed_EN at the Tx block or at LockStateMachine block ?

do i need to define output port to the component Rx and instantiate between the Seed_En and the new port ?

do i need to define input port to the component Tx and instantiate between the Seed_En and the new port ?

btw - every component and sub block is different file at the project and there is Top file that define the I/O 's and there is TestBench file

for the project for simulation.

Thanks .

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Inside component "RX" you would write:

    entity RX...

    seed_EN_out : out std_logic;

    ...

    architecture...

    signal seed_EN : std_logic;

    begin

    ...

    lock_unit : entity work.lockstatemachine

    port map(...

    seed_EN => seed_EN,

    ...

    pn_unit : entity work.pngeneratorrx

    port map(...

    seed_EN => seed_EN,

    end architecture...
  • Altera_Forum's avatar
    Altera_Forum
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    did you mean at the instantiate of :

    ...

    lock_unit : entity work.lockstatemachine

    port map(...

    seed_EN_out => seed_EN,

    ...

    pn_unit : entity work.pngeneratorrx

    port map(...

    seed_EN_out => seed_EN,

    end architecture...

    do i need to define seed_En as input port at the entities: lockstatemachine,pngeneratorrx ?

    ---------------------------------------------------------------------------------------------

    At the second entity - Tx ,

    do i need to define seed_En_in as input port and instantiate between the Seed_En and the new port ?

    Thanks .
  • Altera_Forum's avatar
    Altera_Forum
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    seed_EN is juist a wire connecting the seed_EN_out ports of the two entites. It would be declared as an internal signal in the design file that instantiates the two entites.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    o.k ,

    i will define seed_EN_out as output port from lockstatemachine , but should i define seed_En_in as input port at the entities:pngeneratortx,pngeneratorrx ?

    and then instantiate : seed_EN_out => seed_EN_in ?

    if not , how will seed_EN be connection between lockstatemachine and the two entities ?