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Altera_Forum
Honored Contributor
12 years agoInside component "RX" you would write:
entity RX... seed_EN_out : out std_logic; ... architecture... signal seed_EN : std_logic; begin ... lock_unit : entity work.lockstatemachine port map(... seed_EN => seed_EN, ... pn_unit : entity work.pngeneratorrx port map(... seed_EN => seed_EN, end architecture...