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Honored Contributor
18 years agoAs said, Cyclone II doesn't support chaining of PLLs as you can do e. g. with Cyclone III.
For this reason, I usually routed the main clock input "all around" the FPGA in Cyclone II designs. If you need a PLL function without strict timing requirements, you can probably output it to a pin next a dedicated clock input and route it through pins. A routing delay could be compensated by PLL phase shift.