Confusing cells number while compiling

When I compile below code in Quartus 8.1 Web Edition for synthesis on Altera DE2-70, I get 32 logic elements in Compilation Report.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic (
	reg_size : natural := 32
	);
port (
	a : in std_logic_vector (reg_size - 1 downto 0);
	b : in std_logic_vector (reg_size - 1 downto 0);
	s : out std_logic_vector (reg_size - 1 downto 0)
	);
end adder;
architecture rtl of adder is	
begin
	s <= a + b;
end rtl;

But when compile much bigger code, I get 0 logic elements.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scaler is
generic (
	reg_size : natural := 32  -- input/output register width
	);
port (
	a : in std_logic_vector (reg_size - 1 downto 0);
	s : out std_logic_vector (reg_size - 1 downto 0)
	);
end scaler;
architecture rtl of scaler is
	type reg_array is array(natural range<>) of std_logic_vector(reg_size - 1 downto 0);
	signal adder_in : reg_array(0 to 14);
	signal adder_out : reg_array(0 to 15);	
begin
	adder_in(0)(reg_size - 2 downto 0) <= a(reg_size - 1 downto 1);
	adder_in(0)(reg_size - 1) <= a(reg_size - 1);
	
	adder_out(0) <= a +	adder_in(0);		
	
	adder_in(1)(reg_size - 3 downto 0) <= adder_out(0)(reg_size - 1 downto 2);
	
	gen_adder_in_1 : for i in reg_size - 2 to reg_size - 1
	generate
		adder_in(1)(i) <= adder_out(0)(reg_size - 1);
	end generate;
		
	adder_in(1) <= a + adder_out(1);	
	
	adder_in(2)(reg_size - 2 downto 0) <= adder_out(1)(reg_size - 1 downto 1);
	adder_in(2)(reg_size - 1) <= adder_out(1)(reg_size - 1);
						
	adder_in(2) <= a + adder_out(2);
			
	adder_in(3)(reg_size - 3 downto 0) <= adder_out(2)(reg_size - 1 downto 2);
	
	gen_adder_in_3 : for i in reg_size - 2 to reg_size - 1
	generate
		adder_in(3)(i) <= adder_out(2)(reg_size - 1);
	end generate;
	
	adder_in(3) <= a + adder_out(3);	
	
	adder_in(4)(reg_size - 2 downto 0) <= adder_out(3)(reg_size - 1 downto 1);
	adder_in(4)(reg_size - 1) <= adder_out(3)(reg_size - 1);
		
	adder_in(4) <= a + adder_out(4);
		
	adder_in(5)(reg_size - 2 downto 0) <= adder_out(4)(reg_size - 1 downto 1);
	adder_in(5)(reg_size - 1) <= adder_out(4)(reg_size - 1);
		
	adder_in(5) <= a + adder_out(5);
		
	adder_in(6)(reg_size - 4 downto 0) <= adder_out(5)(reg_size - 1 downto 3);
	
	gen_adder_in_6 : for i in reg_size - 3 to reg_size - 1
	generate
		adder_in(6)(i) <= adder_out(5)(reg_size - 1);
	end generate;
	
	adder_in(6) <= a + adder_out(6);	
	
	adder_in(7)(reg_size - 3 downto 0) <= adder_out(6)(reg_size - 1 downto 2);
	
	gen_adder_in_7 : for i in reg_size - 2 to reg_size - 1
	generate
		adder_in(7)(i) <= adder_out(6)(reg_size - 1);
	end generate;
	
	adder_in(7) <= a + adder_out(7);
		
	adder_in(8)(reg_size - 2 downto 0) <= adder_out(7)(reg_size - 1 downto 1);
	adder_in(8)(reg_size - 1) <= adder_out(7)(reg_size - 1);
	
	adder_in(8) <= a + adder_out(8);
		
	adder_in(9)(reg_size - 2 downto 0) <= adder_out(8)(reg_size - 1 downto 1);
	adder_in(9)(reg_size - 1) <= adder_out(8)(reg_size - 1);
	
	adder_in(9) <= a + adder_out(9);	
	
	adder_in(10)(reg_size - 3 downto 0) <= adder_out(9)(reg_size - 1 downto 2);
	
	gen_adder_in_10 : for i in reg_size - 2 to reg_size - 1
	generate
		adder_in(10)(i) <= adder_out(9)(reg_size - 1);
	end generate;
	
	adder_in(10) <= a + adder_out(10);	
	
	adder_in(11)(reg_size - 2 downto 0) <= adder_out(10)(reg_size - 1 downto 1);
	adder_in(11)(reg_size - 1) <= adder_out(10)(reg_size - 1);
	
	adder_in(11) <= a + adder_out(11);
	
	adder_in(12)(reg_size - 3 downto 0) <= adder_out(11)(reg_size - 1 downto 2);
	
	gen_adder_in_12 : for i in reg_size - 2 to reg_size - 1
	generate
		adder_in(12)(i) <= adder_out(11)(reg_size - 1);
	end generate;
	
	adder_in(12) <= a + adder_out(12);
	
	adder_in(13)(reg_size - 2 downto 0) <= adder_out(12)(reg_size - 1 downto 1);
	adder_in(13)(reg_size - 1) <= adder_out(12)(reg_size - 1);
		
	adder_in(13) <= a + adder_out(13);
	
	adder_in(14)(reg_size - 4 downto 0) <= adder_out(13)(reg_size - 1 downto 3);
	
	gen_adder_in_14 : for i in reg_size - 3 to reg_size - 1
	generate
		adder_in(14)(i) <= adder_out(13)(reg_size - 1);
	end generate;
	
	adder_in(14) <= a + adder_out(14);
		
	adder_out(15)(reg_size - 2 downto 0) <= adder_out(14)(reg_size - 1 downto 1);
	adder_out(15)(reg_size - 1) <= adder_out(14)(reg_size - 1);
	
	incrementor : entity work.incrementor
	generic map (
		reg_size => reg_size
	)
	port map (
		adder_out(15),
		adder_out(14)(0),
		s
	);
end rtl;

What is it caused by?

What resources are used in the second example?

Edit: Problem solved. There was a mistake in the code.