Confused in logic!
Hi Helpers!
I am working on a project in which i have to create 8:1 mux using 4:1 mux, I am done with the 4:1 code and then create symbol file which i used for making 8:1 mux .
4:1 code is mentio...
Forum Discussion
sstrell
Super Contributor
Super ContributorWithout seeing the testbench or the waveform, it's hard to figure out what's wrong here.
If A[2] is the enable signal, I'm not sure why you are inverting it going into the upper mux.
And your s0 line (D[2]) is disconnected from the upper mux in the schematic.
I am New to this coding area!
PLEASE help me clear my basics!
Suppose i have a 4:1 mux and have 4bit input i0,i1,i2,i3, (s0,s1)select lines and output Y.
I use two vcc pins A and B to connect with 4:1.
I want to know that when WE USE RTL Simulation It Give random values to the input and check expected output with the current output , It give random value to A and B or i0,i1,i2,i3.
Can anyone help me design or can anyone design 8:1 mux using 4:1 mux?
- RichardT_altera
If you want to design 8:1 mux using 4:1 mux, perhaps the link below may helps.
Let me know if you need further help with this circuit design.https://www.tutorialspoint.com/digital_circuits/digital_circuits_multiplexers.htm
@RichardTanSY_Altera I want to build 8:! mux using only 4:1 mux and i tried everything but always error occur:(
- RichardT_altera
First, you might need to check your design whether it is designed correctly. Like what Strell mentioned, the D2 wire is not connected to s0 in the first 4 mux. Is this expected? Then, check whether the testbench is write correctly.
Are you simulate using Modelsim? Seems to me, "Wrong output to input" error is generated from your testbench and most probably due to design issue, as you got an unexpected output.
You mentioned there is no wave window, have you try to simulate using the flow below, by adding Signals To Wave Window?https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf
