Forum Discussion
DBart1
New Contributor
New ContributorConfused by JTAG tdi constraint in Intel Quartus Prime Timing Analyzer Cookbook
I found the Intel Quartus Prime Timing Analyzer Cookbook here at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf. I tried using the jtag co...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
If this is a system synchronous interface normally the skew between the JTAG clock TCK arriving at the driving device and the FPGA would be used, not the actual delay from the header to the FPGA.
May I understand more about the comment above? Could you elaborate in details?
Thanks.
