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DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
6 years ago

Confused by JTAG tdi constraint in Intel Quartus Prime Timing Analyzer Cookbook

I found the Intel Quartus Prime Timing Analyzer Cookbook here at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf. I tried using the jtag co...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

If this is a system synchronous interface normally the skew between the JTAG clock TCK arriving at the driving device and the FPGA would be used, not the actual delay from the header to the FPGA.

May I understand more about the comment above? Could you elaborate in details?

Thanks.