Configuring the Quartus IP library "RS232 UART, CLK signal

Thanks Vicky for the suggestion. Unfortunately I’m a complete newbie to Quartus. Coming from a KiCAD board design background I want to program FPGAs using .bdf files. (To me Verilog is like programming Web pages by hand in HTML rather than a web page editor).

Anyway, I have a few real basic questions that will hopefully be useful to other new users…

First I don’t understand your answer/suggestion. Sorry.

What I want to do is add a simple old fashioned UART to a board. The University Program|communications “RS232 UART” seems to be exactly what I want. I can in fact get it to my main “FPGA_IO_Board.bdf” window as a block diagram. All the inputs I can provide except I don’t know how to supply the CLK.

I want to run it at say 9600 BAUD. Can I just use my main FPGA clock input pin (50MHz) and via a PLL & counter supply the frequency X16.

The UART parameter Editor gave an error when generating the Verilog saying the clk was undefined. That’s the only error I got. If I supply it (and of course connect up all the other inputs) should the .bdf box work?

BTW I don’t (think) I have the NEOS CPU active/present. I don’t need it for this application. Some of the documentation seems to refer to it. Totally unclear docs to a new user!