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Altera_Forum
Honored Contributor
Honored ContributorConditional assignment statement vs selected assignment statement
Hello, I have some experience with VHDL, but now I am trying to understand the details and not just using the code. What is the difference between the conditional assignment statement an...
Altera_ForumHonored Contributor
Honored ContributorIn your first post, both bits of code will do the same job. The synthesisor should reduce them both to be the same circuit. So yes, you will get a prioritised mux.
with..select will always infer a mux, as all cases must be covered. a <= b when x else y; can infer lots of different circuits.
