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Altera_Forum
Honored Contributor
Honored ContributorConditional assignment statement vs selected assignment statement
Hello, I have some experience with VHDL, but now I am trying to understand the details and not just using the code. What is the difference between the conditional assignment statement an...
Altera_ForumHonored Contributor
Honored ContributorA normal mux you mean that in this case for the with select we obtain an implementation that considers all inputs ? i.e. implemented with a 16-to-1 mux?
But also like this the circuit won't be prioritized no?
