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RHerm1's avatar
RHerm1
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6 years ago

Concatenation operator in a port assignment ?

I'm using Quartus 18.1.1 / Build 646 and have observed a strange behavior with the following VHDL code: meta_data_ram : altsyncram generic map ( ....... ) port map ( address_a => md_...
RHerm1's avatar
RHerm1
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6 years ago

Thanks for your reply,

I'm using VDHL 2008 and the issue is that a wrong value is assigned to the port "address_a". When I assign the same expression to a signal first and then this signal to a port it works!!