Component Library?

Hi. Glad to hear you're getting somewhere

VHDL allows the easy re-use of code. Libraries are set up however you want in your tool, and you can refer to them in your code. You dont actually need to create a library of components, as they already exist in any project.

When instantiating an entity, the best way is via direct instantiation:

my_inst : entity some_library.some_entity
generic map (
  --map generics here
)
port map (
  --map ports here
);

The advantage of this over componant declarations is two fold:

1. You dont have to maintain what is essentially the same thing in two (or more, if you dont make a package of componant declarations) different places (entity declaration and componant declarations). You never need components again.

2. The compiler checks your port maps directly to the entity declaration - so no more getting half way through synthesis before the error is discovered in component/entity mismatch (because of no. one). The error is found in seconds.

The reason you'll see loads of component libraries and examples filled with components is that direct instatiation didnt exist in the first draft of the language, and those examples have lingered for 20 or so years. But its all hunkydory now and theres no problems with direct instantiation - so use it to tidy up your code.

Another thing - within the same library, you can refer to "work", being the local library, so you can easily do:

my_inst : entity work.some_entity

port map (

..etc

Is this what you were after? or anything more I can help with?