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Altera_Forum
Honored Contributor
8 years ago--------------------Update--------------------
My DSP package do not support 16.1.2 and higher version, this is the reason that the strange errors occured. Now I rollback both Quartus and AOC to 16.1.1, the problem has been solved. i ll update the result of this compilation later. Thanks for ur help!.following questions have been solved. ============ Hi, I updated quartus and aoc/aocl to 16.1.2, but there were some strange errors...... I try to compile a simple OpenCL kernel code with aoc -v --report xxx.cl -o xxx.aocx
But the compilation was failed and the quartus_sh_compile showed:
Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Error (15744): In atom 'board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd'
Error (15744): The settings must match one or more of these conditions:
Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != PCIE_GEN3_RX ) OR ( sd_output_off == CLK_DIVRX_14 )
Error (15744): But the following assignments violate the above conditions:
Error (15744): sup_mode = USER_MODE
Error (15744): prot_mode = PCIE_GEN3_RX
Error (15744): sd_output_off = CLK_DIVRX_6
Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run.
Error: design::import_design -file base.qdb -overwrite failed!
Error (23031): Evaluation of Tcl script d:/intelfpga_pro/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 11 errors, 0 warnings
Error: Peak virtual memory: 3998 megabytes
Error: Processing ended: Thu Jun 29 17:53:43 2017
Error: Elapsed time: 00:19:03
Error: Total CPU time (on all processors): 00:19:03
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
Info: Version 16.1.2 Build 203 01/18/2017 SJ Pro Edition
Info: Copyright (C) 2017 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Thu Jun 29 17:34:40 2017
Info: Command: quartus_cdb -t import_compile.tcl
Info: Using INI file c:/Users/xinzhou/altera/test_version_hello/test_result/quartus.ini
Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 509 megabytes
Error: Processing ended: Thu Jun 29 17:53:45 2017
Error: Elapsed time: 00:19:05
Error: Total CPU time (on all processors): 00:00:00 But I have already used customized bsp package. What's more, aocl diagnose also failed and the screen showed:
Using platform: Intel(R) FPGA SDK for OpenCL(TM)
Using Device with name: a10gx : Arria 10 Reference Platform (acla10_ref0)
Using Device from vendor: Intel(R) Corporation
clGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = 4294967296
clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = 4293918720
Memory consumed for internal use = 1048576
Actual maximum buffer size = 4293918720 bytes
Writing 4095 MB to global memory ...
Allocated 1073741824 Bytes host buffer for large transfers
Write speed: 3232.35 MB/s
Reading and verifying 4095 MB from global memory ...
Verification failure at element 280, expected 118 but read back 15e
First failure at address 1008c0
Verification failure at element 281, expected 119 but read back 189
Verification failure at element 282, expected 11a but read back 199
......
Suppressing error output, counting# of errors ...
Read speed: 3232.59 MB/s
Failed write/readback test with 104652 errors
Error: Global memory test failed
Error code: 0
aocl diagnose: failed.
I am totally confused now...... Thanks for your help! --- Quote Start --- "Placement cannot find a legal solution" usually means that you need some resource (RAM, DSP, etc.) on the FPGA, but that resource has been fully used and there is nothing else left. The closest thing I could find to a meaningful error message in the log was this: Error (17937): The inputs to the LAB at location (68,69) exceed the number of legal inputs. This LAB may be locked or have other LAB-level input restrictions. Refer to the submessage(s) for the specific input nodes that do not fit in the LAB. Remove some inputs to this LAB so the number of inputs does not exceed the legal limit. File: c:/intelfpga_pro/16.1/quartus/libraries/megafunctions/altera_counter.sv Line: 59 But I had personally never seen such message before; the message that is printed in the log when you overutilize the Block RAMs is different. Can you please retry the compilation after updating to 16.1.2 and see what happens? Also please add --report to your compilation log and post the area estimation that you receive in stdout after adding that switch. --- Quote End ---