Complex floating-point sequential logic in Verilog

Ah, that makes a lot of sense, both pipeline and constant optimization explanations. I'm gonna try doing something useful with these pipelined megafunctions later.

As a side note, I just noticed that such pipelining would be an ideal way to deal with the massive rasterization a GPU has to work with.

I was thinking of duplicating the rasterization modules so that they could all work on different pixels at the same time, but since they all obviously take more than one clock cycle to complete processing each pixel, pipelining them could drastically improve performance.

Is this an achievable feat for a Verilog newbie? In any case, I would be grateful if you could tell me about good literature to study this.

You're being very instructive and friendly, rbugalho;

thanks a lot,

n2