Complex floating-point sequential logic in Verilog

Hi,

by "fully pipelined", I mean that they take more than one cycle to calculate a result but they can produce results at a rate of 1 per cycle.

For example, with fully pipelined multiplier with a 5 cycle latency you can do this:

cycle 0: input a = x0; input b = y0 ; output = x

cycle 1: input a = x1; input b = y1 ; output = x

cycle 2: input a = x2; input b = y2 ; output = x

....

cycle 5: input a = x5; input b = y5; output = x0 * y0

cycle 6: input a = x6; input b = y6; output = x1 * y1

cycle 7: input a = x7; input b = y7; output = x2 * y2

And as you guessed, no, unlike software compilers, for a number of reasons, the tools will not replace the division by a constant for a multiplication.

On one hand, these are IEEE 754 modules and in that context, division and multiplication by the reciprocal are not 100% equivalent.

On other hand, there are diferences in terms of sequential behaviour.

A 32 bit FP divider requires, IIRC, 20 cycles to produce a result. The tools could, at best, replace it with a multiplication that takes 20 cycles.

The human, on the other hand, can replace it with a multplication that takes just 5 cycles.