Complex floating-point sequential logic in Verilog

Pleased to meet you, rbugalho, and thanks for your answer.

I'm using Altera Quartus II 9.11, Web Edition version. All of the FP megafunctions in my library seem to be non-pipelined (is this what they call it when a module requires more than one clock to do a given task?).

They all ask me to specify "the output latency in clock cycles", like this ALTFP_MULT screenshot shows (it is the same for ALTFP_ADD_SUB and ALTFP_DIV):

img121*imageshack*us/img121/5323/altfpmult.png (replace asterisks by dots)

Am I mistaken to assume that these megafunctions require more than one clock cycle to finish processing?

Btw, LPM_ADD_SUB left me wondering if we aren't using mistaken nomenclature:

img689*imageshack*us/img689/6064/lpmaddsub.png (replace asterisks by dots)

Doesn't "being pipelined" mean "immediately processed", without clock latency (i.e. only obvious digital logic delay)?

Regarding fixed point math, it's certainly something I'll take into consideration. It's just that I'm just curious about all this FP stuff right now, anyway.

-- edit --

I was wondering about your optimization suggestion of changing the division by an equivalent multiplication and came to the conclusion that it should be very, very easy for the analyser/synthesizer to do that for you.

As long as it's a division by a constant value, can't it always infer an equivalent, faster multiplication? If so, then why isn't this already done?

-- edit --

Uh, never mind. I guess Verilog wouldn't know the registers are floating-point, and so that couldn't be done. It would simply do an integer division in that case.. right? Or is there an elegant way around this?

Cheers,

n2

(ps.: [To alteraforum.com] Your non-link & non-image posting policy for newbies and limited number of images permitted per post ****es anyone off entirely; I strongly suggest you to remove such limitations)